1. Field of the Invention
The present invention relates to integrated circuits and particularly to comparators used in high-speed applications.
2. Description of the Related Art
The function of a voltage comparator is to compare the instantaneous value of a signal voltage at one input to that of a voltage, often a reference voltage, at a second input and produce a voltage representing a digital value, i.e., a binary 1 or 0, at the output when one input is higher than the other. FIG. 1a shows the characteristics of a comparator 10 with inputs Vip and Vin and output Vo, where all the signal levels are measured with reference to circuit ground. In this case, when the differential input voltage Vid=Vipxe2x88x92Vin exceeds 0 volts, the output switches from 0 volts, which is binary 0, to Vdd volts, which is binary 1, as shown by the transfer curve.
Offset comparators have a certain built-in offset voltage VT associated with the differential input such that when the differential input signal exceeds this threshold, the output switches binary states. FIG. 1b shows a comparator 15 with a built-in threshold VT. In this case, when the differential input voltage Vid exceeds the offset threshold VT, the output switches binary states. As illustrated in the accompanying transfer curve, the differential input voltage Vid has to exceed the threshold voltage (VT) before the output switches form 0 to Vdd.
Two conventional approaches for establishing this built-in offset voltage are discussed below. The first approach is illustrated in FIG. 2. FIG. 2 is a schematic diagram of an offset comparator that uses a common-mode tracking circuit to provide the threshold voltage VT. The circuit is comprised of an operational amplifier made up of two differential n-channel input transistors 22-23, a tail current source 24, two p-channel load transistors 20-21, a differential offset circuit consisting of two additional differential n-channel input transistors 25-26, a second tail current source 27, and a common-mode tracking circuit 28. The differential input signals, Vip and Vin, are applied to both the operational amplifier""s inputs at the gates of n-channel transistors 22-23 and to the differential inputs of the common-mode tracking circuit 28. The difference in the output signals from the common-mode tracking circuit 28, VB1 and VB2, represents the offset threshold voltage VT. These VB1 and VB2 signals are inputs to the second differential pair consisting of n-channel transistors 25 and 26, respectively. Finally, the drains of transistors 25-26 are coupled to the drains of the operational amplifier differential pair transistors 22-23 to establish an offset.
Thus, in the first approach the desired offset voltage is accomplished by means of adding another differential pair 25-26, with its own separate tail current 27, in parallel to the input differential pair 22-23 of a 0-volt offset comparator. The added pair 25-26 should be identical to the input differential pair 22-23 of the 0-volt offset comparator, as should the tail currents 24, 27. A common-mode tracking circuit 28 is needed to supply the two bias voltages VB1 and VB2. This common-mode tracking circuit is called on to supply the VB1 and VB2 inputs such that VB1xe2x88x92VB2 is equal to the desired offset VT, and at the same time such that VB1 and VB2 have the same common-mode level as the original inputs, Vip and Vin.
The second approach for establishing this built-in offset voltage is illustrated in FIG. 3. This approach uses two resistor networks 31-34 and 35-38 at the inputs of a operational amplifier 30. In this case, each resistor network, 31-34 and 35-38, is connected between the Vdd voltage and circuit ground with voltage taps located between each resistor. In operation, the differential inputs Vip and Vin are connected to taps on the respective resistor networks, while the + and xe2x88x92 differential inputs to the operational amplifier 30 are taken off other resistor network taps to provide the desired offset for the comparator. This circuit has the characteristics of low input-impedance and high power dissipation.
The offset comparators discussed above either have a common-mode tracking circuit, or have low input impedance. The common-mode tracking circuit is very slow and not suitable if the differential input signal has a fast changing common-mode. On the other hand, the resistor network dissipates a great amount of power and gives a low input-impedance characteristic to the comparator. The above-described prior art circuits are also not directly compatible with many low-voltage digital applications and usually need another circuit to step down the output signal to the desired digital levels. Thus, they tend to be slow, dissipate too much power, and are not directly compatible with many low-voltage digital applications; one such example being the USB interface for computers.
What is needed is a high-speed comparator with a high input-impedance characteristic that can track high-speed differential signals with rapidly changing common-mode levels and provide a binary output signal that can directly interface with inputs of low-voltage applications. The invention disclosed herein addresses these needs and provides such a circuit.
In accordance with the present invention there is provided a high-speed differential offset comparator circuit, providing a comparator function at a predetermined offset voltage. The differential offset comparator circuit includes a substantially zero offset comparator circuit having a first and a second differential input. The differential offset comparator circuit also includes a first pre-amplifier circuit and a second pre-amplifier circuit having an output coupled to the first and the second differential input, respectively, of the substantially zero offset comparator circuit. The pre-amplifier circuits are capable of providing a controllable offset to the differential offset comparator circuit. Each pre-amplifier circuit includes a first MOS transistor and a second MOS transistor connected in series to form a first composite transistor having an effective source, gate and drain. The first MOS transistor receives an input of the differential offset comparator circuit at a gate thereof. The second MOS transistor receives a control voltage corresponding to an offset control voltage at a gate thereof. The offset control voltage controls the value of the predetermined offset voltage.
Circuits according to the present invention can track high-speed signals with rapidly changing common-mode levels without the need for a common-mode tracking circuit, while providing a high impedance input.